The present invention relates to a method for manufacturing a fin transistor, and more particularly, to a method for manufacturing a fin transistor in which an etching loss of a spin-on-glass insulation layer used as a material for a field insulation layer is prevented.
When a design rule of a semiconductor device is decreased, channel length and width of a transistor are correspondingly decreased. As a result, the existing planar transistor structure is limited in realizing the threshold voltage required for a highly integrated semiconductor device having a minimum line width of less than 100 nm. To solve this problem a fin transistor has been suggested in which an increase in driving current and a desired operation speed can be obtained through an increase in the channel width.
The fin transistor's structure includes a field insulation that is etched to create an active region having a projected structure, and thus the width of a transistor is increased by the height of the projected active region. The fin transistor's advantages include an increase in the driving current and the operation speed due to an increase in the channel width.
However, a gap-fill between the active regions of a fin transistor becomes difficult as the integration density of a semiconductor device is increased. Therefore, a spin-on-glass insulation layer having superior filling properties is more useful as a gap-filling material than the existing high density plasma (HDP) insulation layer.
However, the spin-on-glass insulation layer has a very high etching speed to a wet solution compared to the existing high density plasma insulation layer. Therefore, as shown in FIG. 1A, much loss A is generated at the wall of the etched spin-on-glass insulation layer 106 when using wet etching to remove an oxide layer 120. Herein, the oxide layer 120 is at least one of a pad oxide that is used to form a trench in an isolation process, a screen oxide that is used to prevent damage in an implantation process, and a native oxide.
Referring to FIGS. 1A and 1B, the loss A of the spin-on-glass insulation layer 106 can result in a shortage B between adjacent gates 140 and a shortage between the gate 140 and a subsequently formed contact plug. The loss A is a factor that lowers the reliability of a semiconductor device since it can result in a shortage B between adjacent gates 140 as well as a shortage between the gate 140 and a subsequently formed contact plug as shown in FIG. 1B.
Further, a distance between the field region may be decreased due to the loss of the spin-on-glass insulation layer, resulting in signal interference from a passing gate disposed in the spin-on-glass insulation layer filled in a field insulation, i.e. a field region to a main gate disposed over an active region is increased during operation of a semiconductor device. Consequently, gate induced drain leakage (GIDL) current is increased thereby reducing the short channel margin of a transistor. For example, in a DRAM device, the data retention time is shortened making normal operation difficult, and thus device yield and reliability are decreased.